spice device model sud35n05-26l vishay siliconix this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number fo r guaranteed specific ation limits. document number: 71659 www.vishay.com 05-jun-04 1 n-channel 55-v (d-s) 175 c mosfet characteristics ? n-channel vertical dmos ? macro model (subcircuit model) ? level 3 mos ? apply for both linear and switching application ? accurate over the ? 55 to 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics description the attached spice model descri bes the typical electrical characteristics of the n-channel ve rtical dmos. the subcircuit model is extracted and optimized over the ? 55 to 125 c temperature ranges under the pulsed 0 to 10v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback c apacitance network is used to model the gate charge characteri stics while avoiding convergence difficulties of the switched c gd model. all model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. subcircuit model schematic
spice device model sud35n05-026l vishay siliconix www.vishay.com document number: 71659 2 05-jun-04 specifications (t j = 25 c unless otherwise noted) parameter symbol test condition simulated data measured data unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.6 v on-state drain current b i d(on) v ds = 5 v, v gs = 5 v 76 a v gs = 10 v, i d = 20 a 0.0176 0.0165 v gs = 10 v, i d = 20 a, t j = 125 c 0.0269 drain-source on-state resistance b r ds(on) v gs = 4.5 v, i d = 15 a 0.0224 0.0215 ? forward voltage b v sd i s = 80 a, v gs = 0 v 0.92 v dynamic a input capacitance c iss 915 885 output capacitance c oss 183 185 reverse transfe r capacitance c rss v gs = 0 v, v ds = 25 v, f = 1 mhz 74 80 pf total gate charge c q g 10 10.5 gate-source charge c q gs 4 4 gate-drain charge c q gd v ds = 25 v, v gs = 5 v, i d = 35 a 4.8 4.8 nc turn-on delay time c t d(on) 11 5 rise time c t r 19 18 turn-off delay time c t d(off) 35 20 fall time c t f v dd = 25 v, r l = 0.30 ? i d ? 35 a, v gen = 10 v, r g = 2.5 ? 39 100 source-drain reverse recovery time t rr i f = 35 a, di/dt = 100 a/ s 28 25 ns notes a. guaranteed by design, not s ubject to production testing. a. pulse test; pulse width 300 s, duty cycle 2%. b. independent of operat ing temperature.
spice device model sud35n05-26l vishay siliconix document number: 71659 www.vishay.com 05-jun-04 3 comparison of model with measured data (t j =25 c unless otherwise noted)
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